tokenquestBY KUBESIMPLIFY
Let’s explore NVIDIA AI infrastructure

Understand the machines behind AI.

Let’s see what happens after you send a prompt. Explore the machines it runs on, follow the work inside a GPU, and learn how one chip becomes part of an AI cluster.

Explore the hardware Try live explainers

No background needed. Explore at your own pace.

Inside the hardware

Take a closer look.

Choose a machine, drag it around, and select a part to see what it does. Try “Guide me” for a short tour.

Hardware studio

GB300 NVL72Blackwell Ultra

Full rack
Preparing your hardware…
Illustrative 3D modelnot exact CAD
Drag to rotate · scroll to zoomTogether
Original TokenQuest learning model · positions and flow timing are illustrative.

What would you like to learn?

Pick a starting point. You can move between these whenever you like.

TokenQuest is independent of NVIDIA. The practice questions are written for this site.

Interactive visual explainers

Tweak the numbers and watch the system react.

Explore 8 production AI infrastructure concepts right here: PagedAttention, the Roofline model, Tensor vs. Pipeline Parallelism, Speculative Decoding, Disaggregated Serving, MIG partitioning, GPUDirect RDMA, and FlashAttention SRAM tiling.

SERVING MEMORY · LIVE ANIMATED EXPLAINER

PagedAttention and continuous batching

Contiguous KV reservation pre-allocates the maximum context length per request, wasting memory on unused future slots. PagedAttention splits the KV cache into fixed-size blocks mapped through a block table so new requests can join as soon as blocks free up.

Tweak parameters live:
Active requests:
Processed tokens/req:
Page block size:
CONTIGUOUS RESERVATIONREQ 1 · MAX 16 RESERVEDREQ 2 · MAX 16 RESERVEDREQ 3 · MAX 16 RESERVEDREQ 4 · MAX 16 RESERVED63% WASTEDPAGED KV BLOCK POOL (4 TOKENS/BLOCK)BLOCK TABLE → PHYSICAL KV PAGESP0·R1P1·R2P2·R3P3·R4P4·R1P5·R2P6·R3P7·R4FREEFREEFREEFREEFREEFREEFREEFREE+4 MORE SEQUENCES FIT
Why it matters: When KV memory is not wasted on empty reserved tails, a serving engine can fit more concurrent requests in the same GPU memory and admit new prompts on every iteration. (Instead of roping off a 12-seat banquet table for every solo diner just in case friends arrive later, seat people at small modular tables and add another table only when their party grows.)
PLAYABLE PREVIEWINTERVIEW TRACKS COMING SOON

AI Infrastructure Interview Arena

Preparing for an AI Infrastructure, ML Systems, or Kubernetes GPU Platform role? Try our live Whiteboard GPU Sizer, diagnose production DCGM & NCCL incidents, and review senior interview flashcards while we build out the full 4-track simulator.

Track 01 · Preview AvailablePreview live

LLM Serving & Inference System Design

Size GPU clusters for 8B to 405B+ models, balance TTFT vs. TPOT SLAs, and design PagedAttention, speculative decoding and disaggregated prefill/decode pipelines.

  • KV cache memory math & GQA/MLA compression
  • Roofline analysis: prefill compute vs. decode bandwidth
  • Disaggregated prefill/decode & KV cache routing
Track 02 · Preview AvailablePreview live

Kubernetes & Multi-Tenant GPU Operations

Architect production Kubernetes GPU clusters with NVIDIA GPU Operator, Dynamic Resource Allocation (DRA), Topology Manager, MIG partitioning and gang scheduling.

  • MIG hardware isolation vs. time-slicing vs. MPS
  • NUMA & PCIe/NVLink topology-aware pod scheduling
  • GPU Operator daemonsets, driver containers & upgrades
Track 03 · Coming SoonComing soon

High-Speed Fabrics & Multi-Node Scale

Design non-blocking rail-optimized InfiniBand and RoCEv2 fabrics, trace NCCL ring/tree collectives, and eliminate PCIe root-complex bottlenecks with GPUDirect RDMA and Storage.

  • NVLink, NVSwitch & Multi-Node NVLink (MNNVL) domains
  • GPUDirect RDMA & GPUDirect Storage (GDS) zero-copy paths
  • RoCEv2 congestion control (PFC, ECN, DCQCN) vs. InfiniBand
Track 04 · Preview AvailablePreview live

Production GPU Incident Triage & Telemetry

Diagnose real-world cluster slowdowns using DCGM Exporter metrics, XID hardware fault codes, thermal clock throttling, straggler detection and NCCL watchdog traces.

  • Correlating DCGM SM occupancy, tensor active & DRAM active
  • Handling XID errors (ECC page retirement, NVLink link flaps)
  • Liquid cooling manifold alerts & thermal power capping
Hands-on labs & arcade

Learn by solving puzzles and running the pipeline.

Jump directly into any of the six interactive quest boards, calculate real 2×2 matrix tiles in the hardware compute lab, or run the 3-lane Token Dash arcade highway.

Learn by playing

Play the inference map

Follow one request with Mira. Watch each step, try it yourself and see what changes inside the GPU.